1. Technical Field
The present invention relates to electronic design automation (EDA). More specifically, the present invention relates to a method and a system for satisfying routing rules during routing of an integrated circuit (IC) chip design.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, including hundreds of millions of transistors, onto a single semiconductor chip. This dramatic increase in semiconductor integration densities has made it considerably more challenging to efficiently perform routing in such a large-scale IC chip.
Routing an integrated circuit (IC) chip involves determining routes for metal wires which electrically connect integrated circuit devices to produce circuits that perform desired functions. Large scale IC chips are typically routed using routing software, which is typically referred to as a “routing system” or “router.”
The routes generated by a router usually need to satisfy a set of foundry design rules. For example, a foundry may specify spacing rules that a design must meet to ensure that the design can be successfully manufactured, e.g., the foundry may specify the minimum distance between two shapes in the circuit design. A circuit design usually cannot be signed-off until all of the foundry design rules are met.
In addition to the foundry rules, a user may also want to satisfy design rules for improving manufacturing yield. For example, moving routing shapes further apart can usually improve the manufacturing yield.
Conventional routing techniques typically treat all rules with equal importance, and will attempt to satisfy all routing rules. Unfortunately, if the system tries to simultaneously satisfy multiple sets of rules (e.g., foundry rules and design-for-manufacturing rules, etc.), the system may never be able to sign-off a circuit design because the rules may conflict with one another (e.g., some of the foundry rules may conflict with some of the design-for-manufacturing rules).